1. Technical Field
This disclosure relates to processors, and more particularly, apparatus and method embodiments for implementing cache allocation policies in a processor.
2. Description of the Related Art
Modern processors often times have a number of processor cores that may share a single cache. For example, while each processor core may have its own level one (L1) cache, a group of processor cores may share a level two (L2) cache. Threads executing on these multiple cores may access the shared cache. Since multiple cores executing multiple threads may be sharing the same cache, there may be competition for some of the cache resources.
In some processors, cache resources may be statically allocated. That is, each core (or thread executing on the various cores) may be assigned to a fixed amount of cache space (e.g., a fixed number of ways may be reserved for each core) equal to each of the other cores. In some embodiments, operating system software may perform the allocation of ways during operation, and may allocate cache space statically or dynamically. Compiler-based cache allocation may also be used, in which a complier creates a map of for the allocation of cache space for a software program operating in an environment where multiple threads are executing and wherein cache allocation may be changed dynamically.